FinMerge - circuits - Tiny circuits DSL

index : circuits

Tiny circuits DSL

jacques@jacquescomeaux.xyz

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Mode	Name	Size
-rw-r--r--	Properties.agda	15848	log plain
-rw-r--r--	Util.agda	1190	log plain

generated by cgit v1.2.3 (git 2.39.1) at 2025-12-14 20:45:55 +0000