diff options
| -rw-r--r-- | blink.s | 39 | ||||
| -rw-r--r-- | pll.s | 14 |
2 files changed, 49 insertions, 4 deletions
@@ -29,6 +29,7 @@ setup_led: .global blink blink: + ldr r1, =SIO_BASE movs r0, 1 lsls r0, 25 1: @@ -36,21 +37,55 @@ blink: bl delay_1s b 1b +.type long_blink, %function +.global long_blink + +long_blink: + push {lr} + ldr r1, =SIO_BASE + movs r0, 1 + lsls r0, 25 + bl delay_1s + str r0, [r1, GPIO_OUT_XOR_OFST] + bl delay_1s + str r0, [r1, GPIO_OUT_XOR_OFST] + bl delay_1s + pop {pc} + .type blinkN, %function .global blinkN blinkN: push {lr} + ldr r1, =SIO_BASE movs r2, 1 lsls r2, 25 tst r0, r0 beq done on_then_off: str r2, [r1, GPIO_OUT_XOR_OFST] - bl delay_1s + bl delay_quick str r2, [r1, GPIO_OUT_XOR_OFST] - bl delay_1s + bl delay_quick subs r0, r0, 1 bne on_then_off done: pop {pc} + +.type blink_hex, %function +.global blink_hex + +blink_hex: + push {lr} + movs r4, r0 + movs r5, 0xf +1: + ands r0, r5 + bl blinkN + lsrs r4, 4 + beq 2f + bl long_blink + movs r0, r4 + b 1b +2: + pop {pc} @@ -63,6 +63,16 @@ vco_lock: delay_1s: ldr r3, =0x1fca055 // 33.3 * 10^6 (one-third of a second at 100MHz) 1: // 3 clock cycle loop - subs r3, r3, 1 // 1 clock cycle + subs r3, 1 // 1 clock cycle bne 1b // 2 clock cycles when taken - mov pc, lr + bx lr + +.type delay_quick, %function +.global delay_quick + +delay_quick: + ldr r3, =0x65b9ab +1: + subs r3, 1 + bne 1b + bx lr |