From 261c210c9c4c1e55103a7af31dfcc539c0e0e5cc Mon Sep 17 00:00:00 2001
From: Jacques Comeaux <jacquesrcomeaux@protonmail.com>
Date: Fri, 19 Jan 2024 16:41:29 -0600
Subject: Add subroutine for printing hexadecimal word
---
Makefile | 17 -------
blink.s | 103 -----------------------------------------
clocks.s | 31 -------------
gpio.s | 23 ----------
hexedit/Makefile | 17 +++++++
hexedit/clocks.s | 31 +++++++++++++
hexedit/gpio.s | 23 ++++++++++
hexedit/hexedit.s | 25 ++++++++++
hexedit/main.s | 16 +++++++
hexedit/pico_ram_only.ld | 13 ++++++
hexedit/uart.s | 116 +++++++++++++++++++++++++++++++++++++++++++++++
hexedit/xosc.s | 23 ++++++++++
main.s | 16 -------
misc/blink.s | 103 +++++++++++++++++++++++++++++++++++++++++
misc/pll.s | 78 +++++++++++++++++++++++++++++++
pico_ram_only.ld | 13 ------
pll.s | 78 -------------------------------
uart.s | 86 -----------------------------------
xosc.s | 23 ----------
19 files changed, 445 insertions(+), 390 deletions(-)
delete mode 100644 Makefile
delete mode 100644 blink.s
delete mode 100644 clocks.s
delete mode 100644 gpio.s
create mode 100644 hexedit/Makefile
create mode 100644 hexedit/clocks.s
create mode 100644 hexedit/gpio.s
create mode 100644 hexedit/hexedit.s
create mode 100644 hexedit/main.s
create mode 100644 hexedit/pico_ram_only.ld
create mode 100644 hexedit/uart.s
create mode 100644 hexedit/xosc.s
delete mode 100644 main.s
create mode 100644 misc/blink.s
create mode 100644 misc/pll.s
delete mode 100644 pico_ram_only.ld
delete mode 100644 pll.s
delete mode 100644 uart.s
delete mode 100644 xosc.s
diff --git a/Makefile b/Makefile
deleted file mode 100644
index 3529884..0000000
--- a/Makefile
+++ /dev/null
@@ -1,17 +0,0 @@
-all: build
-
-build: echo.uf2
-
-echo.uf2: echo.elf
- ./elf2uf2 echo.elf echo.uf2
-
-objects = main.o xosc.o clocks.o gpio.o uart.o
-
-echo.elf: $(objects)
- arm-none-eabi-ld -T pico_ram_only.ld -o echo.elf $(objects)
-
-$(objects): %.o: %.s
- arm-none-eabi-as -o $@ $<
-
-clean:
- rm echo.elf echo.uf2 *.o
diff --git a/blink.s b/blink.s
deleted file mode 100644
index 5b65eb4..0000000
--- a/blink.s
+++ /dev/null
@@ -1,103 +0,0 @@
-.syntax unified
-.cpu cortex-m0plus
-.thumb
-
-.equ IO_BANK0_BASE, 0x40014000
-.equ GPIO25_STATUS, (IO_BANK0_BASE + 0x0c8)
-.equ GPIO25_CTRL, (IO_BANK0_BASE + 0x0cc)
-
-.equ SIO_BASE, 0xd0000000
-.equ GPIO_OUT_SET_OFST, 0x014
-.equ GPIO_OUT_XOR_OFST, 0x01c
-.equ GPIO_OE_SET_OFST, 0x024
-
-.equ ATOMIC_CLEAR, 0x3000
-
-.type setup_led, %function
-.global setup_led
-
-setup_led:
- ldr r1, =GPIO25_CTRL
- movs r0, 5 // SIO function = 5
- str r0, [r1, 0]
- ldr r1, =SIO_BASE
- movs r0, 1
- lsls r0, r0, 25 // GPIO 25 (LED) output enable
- str r0, [r1, GPIO_OE_SET_OFST]
- bx lr
-
-.type led_on, %function
-.global led_on
-
-led_on:
- ldr r1, =SIO_BASE
- movs r0, 1
- lsls r0, 25
- str r0, [r1, GPIO_OUT_SET_OFST]
-1:
- b 1b
-
-.type blink, %function
-.global blink
-
-blink:
- ldr r1, =SIO_BASE
- movs r0, 1
- lsls r0, 25
-1:
- str r0, [r1, GPIO_OUT_XOR_OFST]
- bl delay_1s
- b 1b
-
-.type long_blink, %function
-.global long_blink
-
-long_blink:
- push {lr}
- ldr r1, =SIO_BASE
- movs r0, 1
- lsls r0, 25
- bl delay_1s
- str r0, [r1, GPIO_OUT_XOR_OFST]
- bl delay_1s
- str r0, [r1, GPIO_OUT_XOR_OFST]
- bl delay_1s
- pop {pc}
-
-.type blinkN, %function
-.global blinkN
-
-blinkN:
- push {lr}
- ldr r1, =SIO_BASE
- movs r2, 1
- lsls r2, 25
- tst r0, r0
- beq done
-on_then_off:
- str r2, [r1, GPIO_OUT_XOR_OFST]
- bl delay_quick
- str r2, [r1, GPIO_OUT_XOR_OFST]
- bl delay_quick
- subs r0, r0, 1
- bne on_then_off
-done:
- pop {pc}
-
-.type blink_hex, %function
-.global blink_hex
-
-blink_hex:
- push {lr}
- movs r4, r0
- movs r5, 0xf
-1:
- ands r0, r5
- bl blinkN
- lsrs r4, 4
- beq 2f
- bl long_blink
- movs r0, r4
- b 1b
-2:
- pop {pc}
diff --git a/clocks.s b/clocks.s
deleted file mode 100644
index 83bc9ff..0000000
--- a/clocks.s
+++ /dev/null
@@ -1,31 +0,0 @@
-.syntax unified
-.cpu cortex-m0plus
-.thumb
-
-.equ CLOCKS_BASE, 0x40008000
-.equ CLK_REF_CTRL_OFST, 0x30
-.equ CLK_SYS_CTRL_OFST, 0x3c
-.equ CLK_PERI_CTRL_OFST, 0x48
-
-.type setup_clocks, %function
-.global setup_clocks
-
-setup_clocks:
-
- ldr r1, =CLOCKS_BASE
-
- // Reference clock
- movs r0, 0x2 // src = xosc
- str r0, [r1, CLK_REF_CTRL_OFST]
-
- // System clock
- movs r0, 0x0 // src = clk_ref
- str r0, [r1, CLK_SYS_CTRL_OFST]
-
- // Peripheral clock
- movs r0, 1 // set enable
- lsls r0, 11
- adds r0, 0x4 << 5 // src = xosc
- str r0, [r1, CLK_PERI_CTRL_OFST]
-
- bx lr
diff --git a/gpio.s b/gpio.s
deleted file mode 100644
index 32e2c37..0000000
--- a/gpio.s
+++ /dev/null
@@ -1,23 +0,0 @@
-.syntax unified
-.cpu cortex-m0plus
-.thumb
-
-.equ RESETS_BASE, 0x4000c000
-.equ RESET_OFST, 0x0
-.equ RESET_DONE_OFST, 0x8
-
-.equ ATOMIC_CLEAR, 0x3000
-
-.type setup_gpio, %function
-.global setup_gpio
-
-setup_gpio:
- ldr r1, =(RESETS_BASE + ATOMIC_CLEAR)
- movs r0, 0b1 << 5 // IO_BANK0
- str r0, [r1, RESET_OFST]
- ldr r1, =RESETS_BASE
-1:
- ldr r2, [r1, RESET_DONE_OFST]
- tst r2, r0
- beq 1b
- bx lr
diff --git a/hexedit/Makefile b/hexedit/Makefile
new file mode 100644
index 0000000..95f49ae
--- /dev/null
+++ b/hexedit/Makefile
@@ -0,0 +1,17 @@
+all: build
+
+build: echo.uf2
+
+echo.uf2: echo.elf
+ ../elf/elf2uf2 echo.elf echo.uf2
+
+objects = main.o xosc.o clocks.o gpio.o uart.o
+
+echo.elf: $(objects)
+ arm-none-eabi-ld -T pico_ram_only.ld -o echo.elf $(objects)
+
+$(objects): %.o: %.s
+ arm-none-eabi-as -o $@ $<
+
+clean:
+ rm echo.elf echo.uf2 *.o
diff --git a/hexedit/clocks.s b/hexedit/clocks.s
new file mode 100644
index 0000000..83bc9ff
--- /dev/null
+++ b/hexedit/clocks.s
@@ -0,0 +1,31 @@
+.syntax unified
+.cpu cortex-m0plus
+.thumb
+
+.equ CLOCKS_BASE, 0x40008000
+.equ CLK_REF_CTRL_OFST, 0x30
+.equ CLK_SYS_CTRL_OFST, 0x3c
+.equ CLK_PERI_CTRL_OFST, 0x48
+
+.type setup_clocks, %function
+.global setup_clocks
+
+setup_clocks:
+
+ ldr r1, =CLOCKS_BASE
+
+ // Reference clock
+ movs r0, 0x2 // src = xosc
+ str r0, [r1, CLK_REF_CTRL_OFST]
+
+ // System clock
+ movs r0, 0x0 // src = clk_ref
+ str r0, [r1, CLK_SYS_CTRL_OFST]
+
+ // Peripheral clock
+ movs r0, 1 // set enable
+ lsls r0, 11
+ adds r0, 0x4 << 5 // src = xosc
+ str r0, [r1, CLK_PERI_CTRL_OFST]
+
+ bx lr
diff --git a/hexedit/gpio.s b/hexedit/gpio.s
new file mode 100644
index 0000000..32e2c37
--- /dev/null
+++ b/hexedit/gpio.s
@@ -0,0 +1,23 @@
+.syntax unified
+.cpu cortex-m0plus
+.thumb
+
+.equ RESETS_BASE, 0x4000c000
+.equ RESET_OFST, 0x0
+.equ RESET_DONE_OFST, 0x8
+
+.equ ATOMIC_CLEAR, 0x3000
+
+.type setup_gpio, %function
+.global setup_gpio
+
+setup_gpio:
+ ldr r1, =(RESETS_BASE + ATOMIC_CLEAR)
+ movs r0, 0b1 << 5 // IO_BANK0
+ str r0, [r1, RESET_OFST]
+ ldr r1, =RESETS_BASE
+1:
+ ldr r2, [r1, RESET_DONE_OFST]
+ tst r2, r0
+ beq 1b
+ bx lr
diff --git a/hexedit/hexedit.s b/hexedit/hexedit.s
new file mode 100644
index 0000000..0bc03a9
--- /dev/null
+++ b/hexedit/hexedit.s
@@ -0,0 +1,25 @@
+.syntax unified
+.cpu cortex-m0plus
+.thumb
+
+.type hexedit, %function
+.global hexedit
+
+hexedit:
+ ldr r2, =0x20000100
+ movs r1, 0
+getchar:
+ bl uart_recv
+ cmp r0, 'g
+ beq stop
+ subs r0, '0 // The ASCII char '0'
+ bmi next
+ lsls r1, 4
+ adds r1, r0
+ b getchar
+next:
+ ldr r0, [r2, 0]
+ adds r2, 4
+ b hexedit
+stop:
+ b 0x20000100
diff --git a/hexedit/main.s b/hexedit/main.s
new file mode 100644
index 0000000..5e294d4
--- /dev/null
+++ b/hexedit/main.s
@@ -0,0 +1,16 @@
+.syntax unified
+.cpu cortex-m0plus
+.thumb
+
+.type main, %function
+.global main
+
+main:
+ bl start_xosc
+ bl setup_clocks
+ bl setup_gpio
+ bl setup_uart
+1:
+ bl uart_recv
+ bl uart_send
+ b 1b
diff --git a/hexedit/pico_ram_only.ld b/hexedit/pico_ram_only.ld
new file mode 100644
index 0000000..eb2450e
--- /dev/null
+++ b/hexedit/pico_ram_only.ld
@@ -0,0 +1,13 @@
+ENTRY(main)
+
+MEMORY {
+ FLASH(rx) : ORIGIN = 0x10000000, LENGTH = 2M
+ SRAM(rwx) : ORIGIN = 0x20000000, LENGTH = 264K
+}
+
+SECTIONS {
+ .text : {
+ *(.text)
+ . = ALIGN(4);
+ } > SRAM
+}
diff --git a/hexedit/uart.s b/hexedit/uart.s
new file mode 100644
index 0000000..9804e53
--- /dev/null
+++ b/hexedit/uart.s
@@ -0,0 +1,116 @@
+.syntax unified
+.cpu cortex-m0plus
+.thumb
+
+.equ RESETS_BASE, 0x4000c000
+.equ RESET_OFST, 0x0
+.equ RESET_DONE_OFST, 0x8
+
+.equ IO_BANK0_BASE, 0x40014000
+.equ GPIO0_CTRL_OFST, 0x04
+.equ GPIO1_CTRL_OFST, 0x0c
+
+.equ UART0_BASE, 0x40034000
+.equ UARTDR_OFST, 0x00
+.equ UARTFR_OFST, 0x18
+.equ UARTIBRD_OFST, 0x24
+.equ UARTFBRD_OFST, 0x28
+.equ UARTLCR_H_OFST, 0x2c
+.equ UARTCR_OFST, 0x30
+
+.equ ATOMIC_SET, 0x2000
+.equ ATOMIC_CLEAR, 0x3000
+
+.type setup_uart, %function
+.global setup_uart
+
+setup_uart:
+
+ // Deassert reset
+ ldr r1, =(RESETS_BASE + ATOMIC_CLEAR)
+ movs r0, 0b1 // UART0
+ lsls r0, 22
+ str r0, [r1, RESET_OFST]
+ ldr r1, =RESETS_BASE
+1:
+ ldr r2, [r1, RESET_DONE_OFST]
+ tst r2, r0
+ beq 1b
+
+ // Configure and enable
+ ldr r1, =UART0_BASE
+ movs r0, 6
+ str r0, [r1, UARTIBRD_OFST]
+ movs r0, 33
+ str r0, [r1, UARTFBRD_OFST]
+ movs r0, 0b111 << 4 // 0b11 = word len 8 bits, 0b1 = FIFO enabled
+ str r0, [r1, UARTLCR_H_OFST]
+ ldr r1, =(UART0_BASE + ATOMIC_SET)
+ movs r0, 0b1 // UART enable
+ str r0, [r1, UARTCR_OFST]
+
+ // Configure GPIO 0 and 1 as TX and RX
+ ldr r1, =IO_BANK0_BASE
+ movs r0, 2 // UART function
+ str r0, [r1, GPIO0_CTRL_OFST]
+ str r0, [r1, GPIO1_CTRL_OFST]
+
+ bx lr
+
+.type uart_send, %function
+.global uart_send
+
+uart_send:
+ ldr r1, =UART0_BASE
+ movs r3, 0b1 << 5 // TX FIFO full
+1:
+ ldr r2, [r1, UARTFR_OFST]
+ tst r2, r3
+ bne 1b
+ strb r0, [r1, UARTDR_OFST]
+ bx lr
+
+.type uart_recv, %function
+.global uart_recv
+
+uart_recv:
+ ldr r1, =UART0_BASE
+ movs r3, 0b1 << 4 // RX FIFO empty
+1:
+ ldr r2, [r1, UARTFR_OFST]
+ tst r2, r3
+ bne 1b
+ ldrb r0, [r1, UARTDR_OFST]
+ bx lr
+
+.type send_hex, %function
+.global send_hex
+
+send_hex:
+ push {lr}
+ movs r4, r0
+ movs r0, '0
+ bl uart_send
+ movs r0, 'x
+ bl uart_send
+ movs r5, 8 // eight nibbles in a word
+0:
+ movs r0, 28 // rotate left 4
+ rors r4, r0
+ movs r0, 0xF // lowest nibble mask
+ ands r0, r4
+ cmp r0, 0x9 // number or letter?
+ bhi 1f
+ adds r0, '0
+ b 2f
+1:
+ adds r0, 'A - 0xA
+2:
+ bl uart_send
+ subs r5, 1
+ bne 0b
+ movs r0, '\r
+ bl uart_send
+ movs r0, '\n
+ bl uart_send
+ pop {pc}
diff --git a/hexedit/xosc.s b/hexedit/xosc.s
new file mode 100644
index 0000000..63760da
--- /dev/null
+++ b/hexedit/xosc.s
@@ -0,0 +1,23 @@
+.syntax unified
+.cpu cortex-m0plus
+.thumb
+
+.equ XOSC_BASE, 0x40024000
+.equ CTRL_OFST, 0x0
+.equ STATUS_OFST, 0x4
+.equ STARTUP_OFST, 0xc
+
+.type start_xosc, %function
+.global start_xosc
+
+start_xosc:
+ ldr r1, =XOSC_BASE
+ movs r0, 47 // startup delay for 12Mhz crystal
+ str r0, [r1, STARTUP_OFST]
+ ldr r0, =0x00fabaa0 // enable
+ str r0, [r1, CTRL_OFST]
+1:
+ ldr r0, [r1, STATUS_OFST]
+ lsrs r0, 31 // stable bit
+ beq 1b
+ bx lr
diff --git a/main.s b/main.s
deleted file mode 100644
index 5e294d4..0000000
--- a/main.s
+++ /dev/null
@@ -1,16 +0,0 @@
-.syntax unified
-.cpu cortex-m0plus
-.thumb
-
-.type main, %function
-.global main
-
-main:
- bl start_xosc
- bl setup_clocks
- bl setup_gpio
- bl setup_uart
-1:
- bl uart_recv
- bl uart_send
- b 1b
diff --git a/misc/blink.s b/misc/blink.s
new file mode 100644
index 0000000..46e6eff
--- /dev/null
+++ b/misc/blink.s
@@ -0,0 +1,103 @@
+.syntax unified
+.cpu cortex-m0plus
+.thumb
+
+.equ IO_BANK0_BASE, 0x40014000
+.equ GPIO25_STATUS, (IO_BANK0_BASE + 0x0c8)
+.equ GPIO25_CTRL, (IO_BANK0_BASE + 0x0cc)
+
+.equ SIO_BASE, 0xd0000000
+.equ GPIO_OUT_SET_OFST, 0x014
+.equ GPIO_OUT_XOR_OFST, 0x01c
+.equ GPIO_OE_SET_OFST, 0x024
+
+.equ ATOMIC_CLEAR, 0x3000
+
+.type setup_led, %function
+.global setup_led
+
+setup_led:
+ ldr r1, =GPIO25_CTRL
+ movs r0, 5 // SIO function = 5
+ str r0, [r1, 0]
+ ldr r1, =SIO_BASE
+ movs r0, 1
+ lsls r0, 25 // GPIO 25 (LED) output enable
+ str r0, [r1, GPIO_OE_SET_OFST]
+ bx lr
+
+.type led_on, %function
+.global led_on
+
+led_on:
+ ldr r1, =SIO_BASE
+ movs r0, 1
+ lsls r0, 25
+ str r0, [r1, GPIO_OUT_SET_OFST]
+1:
+ b 1b
+
+.type blink, %function
+.global blink
+
+blink:
+ ldr r1, =SIO_BASE
+ movs r0, 1
+ lsls r0, 25
+1:
+ str r0, [r1, GPIO_OUT_XOR_OFST]
+ bl delay_1s
+ b 1b
+
+.type long_blink, %function
+.global long_blink
+
+long_blink:
+ push {lr}
+ ldr r1, =SIO_BASE
+ movs r0, 1
+ lsls r0, 25
+ bl delay_1s
+ str r0, [r1, GPIO_OUT_XOR_OFST]
+ bl delay_1s
+ str r0, [r1, GPIO_OUT_XOR_OFST]
+ bl delay_1s
+ pop {pc}
+
+.type blinkN, %function
+.global blinkN
+
+blinkN:
+ push {lr}
+ ldr r1, =SIO_BASE
+ movs r2, 1
+ lsls r2, 25
+ tst r0, r0
+ beq done
+on_then_off:
+ str r2, [r1, GPIO_OUT_XOR_OFST]
+ bl delay_quick
+ str r2, [r1, GPIO_OUT_XOR_OFST]
+ bl delay_quick
+ subs r0, 1
+ bne on_then_off
+done:
+ pop {pc}
+
+.type blink_hex, %function
+.global blink_hex
+
+blink_hex:
+ push {lr}
+ movs r4, r0
+ movs r5, 0xf
+1:
+ ands r0, r5
+ bl blinkN
+ lsrs r4, 4
+ beq 2f
+ bl long_blink
+ movs r0, r4
+ b 1b
+2:
+ pop {pc}
diff --git a/misc/pll.s b/misc/pll.s
new file mode 100644
index 0000000..faeacb1
--- /dev/null
+++ b/misc/pll.s
@@ -0,0 +1,78 @@
+.syntax unified
+.cpu cortex-m0plus
+.thumb
+
+.equ RESETS_BASE, 0x4000c000
+.equ RESET_OFST, 0x0
+.equ RESET_DONE_OFST, 0x8
+
+.equ PLL_SYS_BASE, 0x40028000
+.equ CS_OFST, 0x0
+.equ PWR_OFST, 0x4
+.equ FBDIV_INT_OFST, 0x8
+.equ PRIM_OFST, 0xc
+
+.equ ATOMIC_CLEAR, 0x3000
+
+.type start_pll, %function
+.global start_pll
+
+// configure pll_sys for 100MHz
+start_pll:
+ // clear reset
+ ldr r1, =(RESETS_BASE + ATOMIC_CLEAR)
+ movs r0, 1
+ lsls r0, 12 // pll_sys is bit 12
+ str r0, [r1, RESET_OFST]
+ ldr r1, =RESETS_BASE
+1:
+ ldr r2, [r1, RESET_DONE_OFST]
+ tst r0, r2 // pll_sys is still bit 12
+ // wait for reset done
+ beq 1b
+ // set pls_sys feedback divider to 100
+ ldr r1, =PLL_SYS_BASE
+ movs r0, 100 // FBDIV = 100
+ str r0, [r1, FBDIV_INT_OFST]
+ // set pl_sys post dividers to 12 (6 * 2)
+ ldr r1, =PLL_SYS_BASE
+ movs r0, 6 // POSTDIV1 = 6
+ lsls r0, 4
+ adds r0, 2 // POSTDIV2 = 2
+ lsls r0, 12
+ str r0, [r1, PRIM_OFST]
+ // turn on main power and VCO
+ ldr r1, =(PLL_SYS_BASE + ATOMIC_CLEAR)
+ movs r0, 0x21 // power and VCO (bits 0 and 5)
+ str r0, [r1, PWR_OFST]
+ // wait for VCO to lock
+ ldr r1, =PLL_SYS_BASE
+vco_lock:
+ ldr r2, [r1, CS_OFST]
+ lsrs r2, 31
+ beq vco_lock
+ // turn on post divider power
+ ldr r1, =(PLL_SYS_BASE + ATOMIC_CLEAR)
+ movs r0, 0x8 // postdiv (bit 3)
+ str r0, [r1, PWR_OFST]
+ bx lr
+
+.type delay_1s, %function
+.global delay_1s
+
+delay_1s:
+ ldr r3, =0x1fca055 // 33.3 * 10^6 (one-third of a second at 100MHz)
+1: // 3 clock cycle loop
+ subs r3, 1 // 1 clock cycle
+ bne 1b // 2 clock cycles when taken
+ bx lr
+
+.type delay_quick, %function
+.global delay_quick
+
+delay_quick:
+ ldr r3, =0x65b9ab
+1:
+ subs r3, 1
+ bne 1b
+ bx lr
diff --git a/pico_ram_only.ld b/pico_ram_only.ld
deleted file mode 100644
index eb2450e..0000000
--- a/pico_ram_only.ld
+++ /dev/null
@@ -1,13 +0,0 @@
-ENTRY(main)
-
-MEMORY {
- FLASH(rx) : ORIGIN = 0x10000000, LENGTH = 2M
- SRAM(rwx) : ORIGIN = 0x20000000, LENGTH = 264K
-}
-
-SECTIONS {
- .text : {
- *(.text)
- . = ALIGN(4);
- } > SRAM
-}
diff --git a/pll.s b/pll.s
deleted file mode 100644
index bab31f2..0000000
--- a/pll.s
+++ /dev/null
@@ -1,78 +0,0 @@
-.syntax unified
-.cpu cortex-m0plus
-.thumb
-
-.equ RESETS_BASE, 0x4000c000
-.equ RESET_OFST, 0x0
-.equ RESET_DONE_OFST, 0x8
-
-.equ PLL_SYS_BASE, 0x40028000
-.equ CS_OFST, 0x0
-.equ PWR_OFST, 0x4
-.equ FBDIV_INT_OFST, 0x8
-.equ PRIM_OFST, 0xc
-
-.equ ATOMIC_CLEAR, 0x3000
-
-.type start_pll, %function
-.global start_pll
-
-// configure pll_sys for 100MHz
-start_pll:
- // clear reset
- ldr r1, =(RESETS_BASE + ATOMIC_CLEAR)
- movs r0, 1
- lsls r0, 12 // pll_sys is bit 12
- str r0, [r1, RESET_OFST]
- ldr r1, =RESETS_BASE
-1:
- ldr r2, [r1, RESET_DONE_OFST]
- tst r0, r2 // pll_sys is still bit 12
- // wait for reset done
- beq 1b
- // set pls_sys feedback divider to 100
- ldr r1, =PLL_SYS_BASE
- movs r0, 100 // FBDIV = 100
- str r0, [r1, FBDIV_INT_OFST]
- // set pl_sys post dividers to 12 (6 * 2)
- ldr r1, =PLL_SYS_BASE
- movs r0, 6 // POSTDIV1 = 6
- lsls r0, r0, 4
- adds r0, r0, 2 // POSTDIV2 = 2
- lsls r0, r0, 12
- str r0, [r1, PRIM_OFST]
- // turn on main power and VCO
- ldr r1, =(PLL_SYS_BASE + ATOMIC_CLEAR)
- movs r0, 0x21 // power and VCO (bits 0 and 5)
- str r0, [r1, PWR_OFST]
- // wait for VCO to lock
- ldr r1, =PLL_SYS_BASE
-vco_lock:
- ldr r2, [r1, CS_OFST]
- lsrs r2, r2, 31
- beq vco_lock
- // turn on post divider power
- ldr r1, =(PLL_SYS_BASE + ATOMIC_CLEAR)
- movs r0, 0x8 // postdiv (bit 3)
- str r0, [r1, PWR_OFST]
- bx lr
-
-.type delay_1s, %function
-.global delay_1s
-
-delay_1s:
- ldr r3, =0x1fca055 // 33.3 * 10^6 (one-third of a second at 100MHz)
-1: // 3 clock cycle loop
- subs r3, 1 // 1 clock cycle
- bne 1b // 2 clock cycles when taken
- bx lr
-
-.type delay_quick, %function
-.global delay_quick
-
-delay_quick:
- ldr r3, =0x65b9ab
-1:
- subs r3, 1
- bne 1b
- bx lr
diff --git a/uart.s b/uart.s
deleted file mode 100644
index 19a2882..0000000
--- a/uart.s
+++ /dev/null
@@ -1,86 +0,0 @@
-.syntax unified
-.cpu cortex-m0plus
-.thumb
-
-.equ RESETS_BASE, 0x4000c000
-.equ RESET_OFST, 0x0
-.equ RESET_DONE_OFST, 0x8
-
-.equ IO_BANK0_BASE, 0x40014000
-.equ GPIO0_CTRL_OFST, 0x04
-.equ GPIO1_CTRL_OFST, 0x0c
-
-.equ UART0_BASE, 0x40034000
-.equ UARTDR_OFST, 0x00
-.equ UARTFR_OFST, 0x18
-.equ UARTIBRD_OFST, 0x24
-.equ UARTFBRD_OFST, 0x28
-.equ UARTLCR_H_OFST, 0x2c
-.equ UARTCR_OFST, 0x30
-
-.equ ATOMIC_SET, 0x2000
-.equ ATOMIC_CLEAR, 0x3000
-
-.type setup_uart, %function
-.global setup_uart
-
-setup_uart:
-
- // Deassert reset
- ldr r1, =(RESETS_BASE + ATOMIC_CLEAR)
- movs r0, 0b1 // UART0
- lsls r0, 22
- str r0, [r1, RESET_OFST]
- ldr r1, =RESETS_BASE
-1:
- ldr r2, [r1, RESET_DONE_OFST]
- tst r2, r0
- beq 1b
-
- // Configure and enable
- ldr r1, =UART0_BASE
- movs r0, 6
- str r0, [r1, UARTIBRD_OFST]
- movs r0, 33
- str r0, [r1, UARTFBRD_OFST]
- movs r0, 0b111 << 4 // 0b11 = word len 8 bits, 0b1 = FIFO enabled
- str r0, [r1, UARTLCR_H_OFST]
- ldr r1, =(UART0_BASE + ATOMIC_SET)
- movs r0, 0b1 // UART enable
- str r0, [r1, UARTCR_OFST]
-
- // Configure GPIO 0 and 1 as TX and RX
- ldr r1, =IO_BANK0_BASE
- movs r0, 2 // UART function
- str r0, [r1, GPIO0_CTRL_OFST]
- str r0, [r1, GPIO1_CTRL_OFST]
-
- bx lr
-
-.type uart_send, %function
-.global uart_send
-
-uart_send:
- ldr r1, =UART0_BASE
-1:
- ldr r2, [r1, UARTFR_OFST]
- movs r3, 0b1 << 5 // TX FIFO full
- tst r2, r3
- bne 1b
- movs r2, 0xff
- ands r0, r2
- str r0, [r1, UARTDR_OFST]
- bx lr
-
-.type uart_recv, %function
-.global uart_recv
-
-uart_recv:
- ldr r1, =UART0_BASE
-1:
- ldr r2, [r1, UARTFR_OFST]
- movs r3, 0b1 << 4 // RX FIFO empty
- tst r2, r3
- bne 1b
- ldr r0, [r1, UARTDR_OFST]
- bx lr
diff --git a/xosc.s b/xosc.s
deleted file mode 100644
index 883200f..0000000
--- a/xosc.s
+++ /dev/null
@@ -1,23 +0,0 @@
-.syntax unified
-.cpu cortex-m0plus
-.thumb
-
-.equ XOSC_BASE, 0x40024000
-.equ CTRL_OFST, 0x0
-.equ STATUS_OFST, 0x4
-.equ STARTUP_OFST, 0xc
-
-.type start_xosc, %function
-.global start_xosc
-
-start_xosc:
- ldr r1, =XOSC_BASE
- movs r0, 47 // startup delay = 47 for 12Mhz crystal
- str r0, [r1, STARTUP_OFST]
- ldr r0, =0x00fabaa0 // enable
- str r0, [r1, CTRL_OFST]
-1:
- ldr r0, [r1, STATUS_OFST]
- lsrs r0, 31 // stable bit
- beq 1b
- bx lr
--
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