From 42479c459305481591cdafb6d6d0e1979564f1f0 Mon Sep 17 00:00:00 2001
From: Jacques Comeaux <jacquesrcomeaux@protonmail.com>
Date: Sun, 17 Dec 2023 14:57:23 -0600
Subject: Initial commit

---
 .gitignore       |  3 +++
 Makefile         | 20 +++++++++++++++++++
 blink.s          | 58 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 pico_ram_only.ld | 13 +++++++++++++
 4 files changed, 94 insertions(+)
 create mode 100644 .gitignore
 create mode 100644 Makefile
 create mode 100644 blink.s
 create mode 100644 pico_ram_only.ld

diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..4924391
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,3 @@
+*.elf
+*.o
+*.uf2
diff --git a/Makefile b/Makefile
new file mode 100644
index 0000000..3a94707
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,20 @@
+all: build
+
+build: blink.uf2
+
+# convert ELF file to UF2 file
+blink.uf2: blink.elf
+	elf2uf2 blink.elf blink.uf2
+
+# compile
+blink.elf: blink.o
+	arm-none-eabi-ld -T pico_ram_only.ld -o blink.elf blink.o
+
+blink.o: blink.s
+	arm-none-eabi-as -o blink.o blink.s
+
+# flash: build/blink.uf2
+# 	cp build/blink.uf2 /Volumes/RPI-RP2
+
+clean:
+	rm blink.elf blink.uf2 blink.o
diff --git a/blink.s b/blink.s
new file mode 100644
index 0000000..34c4086
--- /dev/null
+++ b/blink.s
@@ -0,0 +1,58 @@
+.syntax unified
+.cpu cortex-m0plus
+.thumb
+
+.equ RESETS_BASE,     0x4000c000
+.equ RESET_OFST,      0x0
+.equ RESET_DONE_OFST, 0x8
+
+.equ IO_BANK0_BASE,   0x40014000
+.equ GPIO25_STATUS,   (IO_BANK0_BASE + 0x0c8)
+.equ GPIO25_CTRL,     (IO_BANK0_BASE + 0x0cc)
+
+.equ SIO_BASE,          0xd0000000
+.equ GPIO_OE_SET_OFST,  0x024
+.equ GPIO_OUT_XOR_OFST, 0x01c
+
+.equ ATOMIC_CLEAR,    0x3000
+
+.type main, %function
+.global main
+main:
+
+  // Deassert GPIO reset
+  ldr r1, =(RESETS_BASE + ATOMIC_CLEAR)
+  movs r0, 0x20                           // IO_BANK0 is bit 5
+  str r0, [r1, RESET_OFST]
+
+  // Wait for GPIO reset to finish
+  ldr r1, =RESETS_BASE
+1:
+  ldr r2, [r1, RESET_DONE_OFST]
+  tst r0, r2
+  beq 1b
+
+  // Set GPIO25 function to SIO
+  ldr r1, =GPIO25_CTRL
+  movs r0, #5
+  str r0, [r1, #0]
+
+  ldr r1, =SIO_BASE
+
+  // Set output enable for GPIO 25
+  movs r0, #1
+  lsls r0, r0, #25
+  str r0, [r1, GPIO_OE_SET_OFST]
+
+loop:
+
+  // Toggle output level for GPIO 25
+  str r0, [r1, GPIO_OUT_XOR_OFST]
+
+  // Delay
+  ldr r2, =400000
+1:
+  subs r2, r2, #1
+  bne 1b
+
+  b loop
diff --git a/pico_ram_only.ld b/pico_ram_only.ld
new file mode 100644
index 0000000..eb2450e
--- /dev/null
+++ b/pico_ram_only.ld
@@ -0,0 +1,13 @@
+ENTRY(main)
+
+MEMORY {
+  FLASH(rx) : ORIGIN = 0x10000000, LENGTH = 2M
+  SRAM(rwx) : ORIGIN = 0x20000000, LENGTH = 264K
+}
+
+SECTIONS {
+  .text : {
+    *(.text)
+    . = ALIGN(4);
+  } > SRAM
+}
-- 
cgit v1.2.3