From 7388c270069c2d1418539bca1d2789a6d468ecc2 Mon Sep 17 00:00:00 2001 From: Jacques Comeaux Date: Mon, 20 May 2024 23:19:14 -0500 Subject: Make shared object for setup routines --- setup/Makefile | 14 ++++++++++++++ setup/clocks.s | 31 ++++++++++++++++++++++++++++++ setup/combine.ld | 5 +++++ setup/gpio.s | 23 ++++++++++++++++++++++ setup/uart.s | 58 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ setup/xosc.s | 23 ++++++++++++++++++++++ 6 files changed, 154 insertions(+) create mode 100644 setup/Makefile create mode 100644 setup/clocks.s create mode 100644 setup/combine.ld create mode 100644 setup/gpio.s create mode 100644 setup/uart.s create mode 100644 setup/xosc.s (limited to 'setup') diff --git a/setup/Makefile b/setup/Makefile new file mode 100644 index 0000000..5b6dbe7 --- /dev/null +++ b/setup/Makefile @@ -0,0 +1,14 @@ +all: build + +build: setup.so + +objects = xosc.o clocks.o gpio.o uart.o + +setup.so: $(objects) + arm-none-eabi-ld -r -T combine.ld -o setup.so $(objects) + +$(objects): %.o: %.s + arm-none-eabi-as -o $@ $< + +clean: + rm setup.so *.o diff --git a/setup/clocks.s b/setup/clocks.s new file mode 100644 index 0000000..83bc9ff --- /dev/null +++ b/setup/clocks.s @@ -0,0 +1,31 @@ +.syntax unified +.cpu cortex-m0plus +.thumb + +.equ CLOCKS_BASE, 0x40008000 +.equ CLK_REF_CTRL_OFST, 0x30 +.equ CLK_SYS_CTRL_OFST, 0x3c +.equ CLK_PERI_CTRL_OFST, 0x48 + +.type setup_clocks, %function +.global setup_clocks + +setup_clocks: + + ldr r1, =CLOCKS_BASE + + // Reference clock + movs r0, 0x2 // src = xosc + str r0, [r1, CLK_REF_CTRL_OFST] + + // System clock + movs r0, 0x0 // src = clk_ref + str r0, [r1, CLK_SYS_CTRL_OFST] + + // Peripheral clock + movs r0, 1 // set enable + lsls r0, 11 + adds r0, 0x4 << 5 // src = xosc + str r0, [r1, CLK_PERI_CTRL_OFST] + + bx lr diff --git a/setup/combine.ld b/setup/combine.ld new file mode 100644 index 0000000..29a70f0 --- /dev/null +++ b/setup/combine.ld @@ -0,0 +1,5 @@ +SECTIONS { + .text : { + *(.text) + } +} diff --git a/setup/gpio.s b/setup/gpio.s new file mode 100644 index 0000000..32e2c37 --- /dev/null +++ b/setup/gpio.s @@ -0,0 +1,23 @@ +.syntax unified +.cpu cortex-m0plus +.thumb + +.equ RESETS_BASE, 0x4000c000 +.equ RESET_OFST, 0x0 +.equ RESET_DONE_OFST, 0x8 + +.equ ATOMIC_CLEAR, 0x3000 + +.type setup_gpio, %function +.global setup_gpio + +setup_gpio: + ldr r1, =(RESETS_BASE + ATOMIC_CLEAR) + movs r0, 0b1 << 5 // IO_BANK0 + str r0, [r1, RESET_OFST] + ldr r1, =RESETS_BASE +1: + ldr r2, [r1, RESET_DONE_OFST] + tst r2, r0 + beq 1b + bx lr diff --git a/setup/uart.s b/setup/uart.s new file mode 100644 index 0000000..d4b81d2 --- /dev/null +++ b/setup/uart.s @@ -0,0 +1,58 @@ +.syntax unified +.cpu cortex-m0plus +.thumb + +.equ RESETS_BASE, 0x4000c000 +.equ RESET_OFST, 0x0 +.equ RESET_DONE_OFST, 0x8 + +.equ IO_BANK0_BASE, 0x40014000 +.equ GPIO0_CTRL_OFST, 0x04 +.equ GPIO1_CTRL_OFST, 0x0c + +.equ UART0_BASE, 0x40034000 +.equ UARTDR_OFST, 0x00 +.equ UARTFR_OFST, 0x18 +.equ UARTIBRD_OFST, 0x24 +.equ UARTFBRD_OFST, 0x28 +.equ UARTLCR_H_OFST, 0x2c +.equ UARTCR_OFST, 0x30 + +.equ ATOMIC_SET, 0x2000 +.equ ATOMIC_CLEAR, 0x3000 + +.type setup_uart, %function +.global setup_uart + +setup_uart: + + // Deassert reset + ldr r1, =(RESETS_BASE + ATOMIC_CLEAR) + movs r0, 0b1 // UART0 + lsls r0, 22 + str r0, [r1, RESET_OFST] + ldr r1, =RESETS_BASE +1: + ldr r2, [r1, RESET_DONE_OFST] + tst r2, r0 + beq 1b + + // Configure and enable + ldr r1, =UART0_BASE + movs r0, 6 + str r0, [r1, UARTIBRD_OFST] + movs r0, 33 + str r0, [r1, UARTFBRD_OFST] + movs r0, 0b111 << 4 // 0b11 = word len 8 bits, 0b1 = FIFO enabled + str r0, [r1, UARTLCR_H_OFST] + ldr r1, =(UART0_BASE + ATOMIC_SET) + movs r0, 0b1 // UART enable + str r0, [r1, UARTCR_OFST] + + // Configure GPIO 0 and 1 as TX and RX + ldr r1, =IO_BANK0_BASE + movs r0, 2 // UART function + str r0, [r1, GPIO0_CTRL_OFST] + str r0, [r1, GPIO1_CTRL_OFST] + + bx lr diff --git a/setup/xosc.s b/setup/xosc.s new file mode 100644 index 0000000..63760da --- /dev/null +++ b/setup/xosc.s @@ -0,0 +1,23 @@ +.syntax unified +.cpu cortex-m0plus +.thumb + +.equ XOSC_BASE, 0x40024000 +.equ CTRL_OFST, 0x0 +.equ STATUS_OFST, 0x4 +.equ STARTUP_OFST, 0xc + +.type start_xosc, %function +.global start_xosc + +start_xosc: + ldr r1, =XOSC_BASE + movs r0, 47 // startup delay for 12Mhz crystal + str r0, [r1, STARTUP_OFST] + ldr r0, =0x00fabaa0 // enable + str r0, [r1, CTRL_OFST] +1: + ldr r0, [r1, STATUS_OFST] + lsrs r0, 31 // stable bit + beq 1b + bx lr -- cgit v1.2.3