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authorJacques Comeaux <jacquesrcomeaux@protonmail.com>2023-12-24 23:03:47 -0600
committerJacques Comeaux <jacquesrcomeaux@protonmail.com>2023-12-24 23:03:47 -0600
commitad75550260068087c4351a6a197e10c02fe3b399 (patch)
treeb9d6504843caa03b7aa0e0823672104ec57bfd79
parent8c8569bf9575a4f1077a1b8a61f47d5b4ff55727 (diff)
Add blinkN subroutine
-rw-r--r--blink.s44
-rw-r--r--main.s6
-rw-r--r--pll.s10
3 files changed, 49 insertions, 11 deletions
diff --git a/blink.s b/blink.s
index 3bda498..62b6654 100644
--- a/blink.s
+++ b/blink.s
@@ -12,10 +12,10 @@
.equ ATOMIC_CLEAR, 0x3000
-.type blink, %function
-.global blink
+.type setup_led, %function
+.global setup_led
-blink:
+setup_led:
ldr r1, =GPIO25_CTRL
movs r0, 5 // SIO function = 5
str r0, [r1, 0]
@@ -23,10 +23,34 @@ blink:
movs r0, 1
lsls r0, r0, 25 // GPIO 25 (LED) output enable
str r0, [r1, GPIO_OE_SET_OFST]
-toggle_one_second:
- str r0, [r1, GPIO_OUT_XOR_OFST] // toggle GPIO 25 output level
- ldr r2, =0x1fca055 // 33.3 * 10^6 (one-third of a second at 100MHz)
-1: // 3 clock cycle loop
- subs r2, r2, 1 // 1 clock cycle
- bne 1b // 2 clock cycles when taken
- b toggle_one_second
+ bx lr
+
+.type blink, %function
+.global blink
+
+blink:
+ movs r0, 1
+ lsls r0, 25
+1:
+ str r0, [r1, GPIO_OUT_XOR_OFST]
+ bl delay_1s
+ b 1b
+
+.type blinkN, %function
+.global blinkN
+
+blinkN:
+ push {lr}
+ movs r2, 1
+ lsls r2, 25
+ tst r0, r0
+ beq done
+on_then_off:
+ str r2, [r1, GPIO_OUT_XOR_OFST]
+ bl delay_1s
+ str r2, [r1, GPIO_OUT_XOR_OFST]
+ bl delay_1s
+ subs r0, r0, 1
+ bne on_then_off
+done:
+ pop {pc}
diff --git a/main.s b/main.s
index eb5c8f9..0f137d6 100644
--- a/main.s
+++ b/main.s
@@ -10,4 +10,8 @@ main:
bl start_pll
bl setup_clocks
bl setup_gpio
- b blink
+ bl setup_led
+ movs r0, 3
+ bl blinkN
+stop:
+ b stop
diff --git a/pll.s b/pll.s
index 7458f61..38573f7 100644
--- a/pll.s
+++ b/pll.s
@@ -56,3 +56,13 @@ vco_lock:
movs r0, 0x8 // postdiv (bit 3)
str r0, [r1, PWR_OFST]
bx lr
+
+.type delay_1s, %function
+.global delay_1s
+
+delay_1s:
+ ldr r3, =0x1fca055 // 33.3 * 10^6 (one-third of a second at 100MHz)
+1: // 3 clock cycle loop
+ subs r3, r3, 1 // 1 clock cycle
+ bne 1b // 2 clock cycles when taken
+ mov pc, lr