Rework assembler for simplified instruction set

- Remove commas and brackets from syntax
- Rename opcodes for unambiguous instruction encodings
- Redesign parse instruction encoding
- Implement opcode parser
- Add bit-width restriction to octal parser

1 files changed, 26 insertions, 33 deletions

diff --git a/assembler/register.s b/assembler/register.s
index dd0e1ae..348d8cf 100644
--- a/assembler/register.s
+++ b/assembler/register.s
@@ -1,62 +1,55 @@
-register4:
+.syntax unified
+.cpu cortex-m0plus
+.thumb
+
+.type register, %function
+.global register
+
+register:
   PUSH {LR}
+  MOV R4, R0
+  LSLS R4, 1
+  ADDS R4, ('0 + 1)
 10:
   BL get_char
   MOVS R1, 'R
-  CMPS R0, R1
+  CMP R0, R1
   BNE 10b
+  BL uart_send
 20:
   BL get_char
   MOVS R1, '0
-  CMPS R0, R1
+  CMP R0, R1
   BLO 20b
-  MOVS R1, '9
-  CMPS R0, R1
+  CMP R0, R4
   BHI 20b
+  BL uart_send
   MOVS R1, '1
-  CMPS R0, R1
+  CMP R0, R1
   BNE 30f
+  MOVS R1, '7
+  CMP R4, R1
+  BEQ 30f
 50:
   BL get_char
+  // CMP R0, '  // space is stop char
   BEQ 60f
   MOVS R1, '0
-  CMPS R0, R1
+  CMP R0, R1
   BLO 50b
   MOVS R1, '5
-  CMPS R0, R1
+  CMP R0, R1
   BHI 50b
+  BL uart_send
   ADDS R0, 10
 30:
   SUBS R0, '0
-  MOVS R4, 0
-  ORRS R4, R0
+  MOV R4, R0
 40:
   BL get_char
+  // CMP R0, '  // space is stop char
   BNE 40b
   POP {PC}
 60:
   MOVS R4, 1
   POP {PC}
-
-register3:
-  PUSH {LR}
-10:
-  BL get_char
-  MOVS R1, 'R
-  CMPS R0, R1
-  BNE 10b
-20:
-  BL get_char
-  MOVS R1, '0
-  CMPS R0, R1
-  BLO 20b
-  MOVS R1, '7
-  CMPS R0, R1
-  BHI 20b
-30:
-  SUBS R0, '0
-  MOVS R4, 0
-  ORRS R4, R0
-  BL get_char
-  BNE 40b
-  POP {PC}